1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same wherein, when the semiconductor device is to be self-alignedly formed, first, a base is formed by a selective growth method using a molecular beam epitaxial method, second, a high impurity-concentration region (pedestal ion-implanted portion) is formed in a collector region immediately below an emitter region, and third, a plurality of polysilicon films are used as wiring layers.
2. Description of the Prior Art
First, a bipolar transistor is used in the central component of equipment such as a super computer and an optical communication apparatus requiring a high-speed operation, and the bipolar transistor requires a high-speed operation to operate the equipment at high speed. In order to obtain a high-speed operation, a high-concentration base layer having a very small thickness must be formed, and parasitic capacitances (emitter-base capacitance, base-collector capacitance and collector-substrate capacitance) and parasitic resistances (base resistance, emitter resistance and collector saturation resistance) must be decreased.
In a conventional technique, the base of a bipolar transistor is formed using a molecular beam epitaxial selective growth method (to be referred to as MBE hereinafter) in place of an ion implantation method or a diffusion method. In addition, a bipolar transistor using a so-called SSSB (super self-aligned selectively grown base) structure for a high integration density is proposed. In the SSSB structure, a polysilicon external base electrode and a polysilicon emitter region are formed on an epitaxial substrate self-alignedly with a high-concentration base layer.
FIG. 1 shows a typical example. In FIG. 1, reference numeral 31 denotes a p-type silicon substrate, 32; an n-type (high concentration) collector region; 34, an n-type (low concentration) epitaxial layer; 35, an element isolation region formed by a trench; and 36, a base layer formed by MBE. Reference numerals 37, 38, and 39 respectively denote an emitter layer, an external base layer, and a collector layer each of which is formed by a polysilicon layer. In addition, reference numerals 40, 41, and 42 respectively denote an emitter electrode, a base electrode, and a collector electrode each, of which is formed by a PtSi layer and a tungsten layer.
As an example of forming a base layer using MBE, a method of manufacturing a semiconductor device is disclosed in Japanese Patent Laid-Open No. 1-173642. According to this method, as shown in FIG. 2A, after an n-type buried layer 52 is formed on a p-type silicon substrate 51, an n-type epitaxial layer 53 is stacked on the silicon substrate 51.
As shown in FIG. 2B, a field insulating layer 54, a p-type base extracting polysilicon layer 55, and an SiO.sub.2 film 56 are sequentially stacked on the resultant structure, and a portion serving as an emitter region is etched to expose the n-type epitaxial layer 53.
As shown in FIG. 2C, an Si film is deposited on the entire surface of the resultant structure, and the Si film is partially removed by RIE (Reactive Ion Etching) to form a polysilicon step portion 57. Thereafter, an Si film is selectively epitaxially grown at a portion serving as an emitter region on the n-type epitaxial layer 53 to form a p-type epitaxial base layer 58.
As shown in FIG. 3A, an SiO.sub.2 film is deposited on the entire surface of the resultant structure, and the SiO.sub.2 film is partially removed by RIE to form an SiO.sub.2 insulating step portion 59. Thereafter, an emitter polysilicon layer 60 is formed on the emitter portion, and an n-type impurity is diffused from the emitter polysilicon layer 60 to form an emitter diffused region 61 in the base layer.
As shown in FIG. 3B, after a base contact hole 62 is formed, an emitter electrode 63 and a base electrode 64 are formed by Al deposition, thereby obtaining a super high-speed bipolar transistor.
In the transistor shown in FIG. 1, however, as in the enlarged view of FIG. 4, a base contact width dc (FIG. 5) depends on an undercut amount du obtained when a dielectric film 71 serving as the lowermost layer is etched. Therefore, when a thickness t of the dielectric film 71 is increased to reduce a collector-base capacitance, the contact width dc is disadvantageously increased.
As shown in FIG. 5, since an undercut portion 72 must be buried by the base layer 36 and the polysilicon layer (external base layer) 38 grown when an MBE operation is performed, the thickness t of the dielectric film 71 serving as the lowermost layer must be set to be twice a base width tb. Therefore, in accordance with a decrease in thickness of the base layer 36, the thickness of the dielectric film 71 is decreased to disadvantageously cause an increase in collector-base capacitance.
In the manufacturing method shown in FIGS. 2A to 3B, since the polysilicon step portion 57 is formed such that the etching is performed by RIE, the silicon substrate (the n-type epitaxial layer 53) under the polysilicon step portion 57 is damaged, and the characteristics of the bipolar transistor are considerably degraded disadvantageously.
Second, a pedestal ion implantation is advantageously performed to obtain a high-performance bipolar transistor. According to the pedestal ion implantation, an n.sup.+ -type region in case of an npn transistor is selectively formed immediately below an intrinsic collector by high-energy ion implantation, thereby decreasing a collector series resistance and suppressing a Kirk effect.
The decrease in collector series resistance and the like can also be achieved by increasing the impurity concentration of the whole collector. In this case, however, a base-collector junction capacitance is increased to degrade the performance of the transistor.
In manufacturing a transistor having a so-called two-layered polysilicon film structure in which a base extracting electrode and an emitter extracting electrode are respectively formed by polysilicon films of different layers, pedestal ion implantation is conventionally performed as follows.
That is, openings for forming an emitter and a base are formed using a resist as a mask in a base extracting electrode polysilicon film and an SiO.sub.2 film serving as an interlayer insulator covering the polysilicon film. After the resist is removed, the pedestal ion implantation is performed using the SiO.sub.2 film as a mask.
As described above, however, since the pedestal ion implantation is performed with a high energy, the thickness of the SiO.sub.2 film must be increased under the condition that only the SiO.sub.2 film is used as a mask. However, since the SiO.sub.2 film serving as the an interlayer insulator is not removed, when the thickness of the SiO.sub.2 film is increased, the steps of a contact hole and the like are increased. Therefore, according to the conventional method, a wiring line is frequently disconnected at the step portions, and a high-quality semiconductor device cannot be manufactured.
Third, in a semiconductor device, a plurality of polysilicon films are often formed on a semiconductor substrate. For example, in a semiconductor integrated circuit device including a bipolar transistor and a resistor element, the resistor element is formed by the first layer polysilicon film on the semiconductor substrate, an emitter extracting electrode is formed by the second layer polysilicon film, and an emitter and the like may be formed by performing solid phase diffusion of an impurity from the emitter extracting electrode.
When a resistor element is to be formed by a polysilicon film, annealing is generally performed such that dangling bonds at grain boundary of the polysilicon film are terminated to improve the crystallinity of the polysilicon film. In addition, the annealing is required to perform solid phase diffusion of an impurity from the emitter extracting electrode.
As the above annealing, conventional annealing using a halogen lamp is generally performed. In this annealing, high-temperature rapid annealing can be performed, and a shallow junction is formed while an activation ratio is increased in solid phase diffusion of an impurity. Therefore, a high-performance bipolar transistor having a high-speed operation and low power consumption can be obtained.
However, the beam of the halogen lamp has a wavelength falling within a range of 0.2 to 6.0 .mu.m or more, and a light component having a long wavelength and a high transmittance has a high light intensity. For this reason, the beam reaches the layer under the emitter extracting electrode covered with an insulating film such as an SiO.sub.2 film or the like, and the temperature of the first layer polysilicon film forming the resistor element is increased.
As a result, crystal grains are grown in the first layer polysilicon film, and the growth of the crystal grains depends on the crystallinity of the first layer polysilicon film prior to the growth. However, since the growth of the crystal grains is not easily controlled, the resistance of the resistor element is varied. That is, in the conventional annealing using the halogen lamp, a high-speed bipolar transistor and a highly accurate resistor element cannot be easily obtained at the same time.